1. Field of the Invention
The present invention relates generally to methods of fabricating electronic component packages and the resulting structures. More particularly, the present invention relates to a method of fabricating a bumped chip package and the resulting structures.
2. Description of the Related Art
During the formation of wafer level chip packages, a seed layer is blanket formed across the entire substrate. This seed layer is used to plate a conductive circuit pattern. After plating of the conductive circuit pattern, the un-plated portions of the seed layer are removed using chemical etching.
However, chemical etching results in the generation of hazardous waste, which must be treated or disposed of. Treatment or disposal of hazardous waste is expensive and unfavorable for the environment.
Further, during the chemical etching of the seed layer, the circuit pattern is also etched to some degree. This inevitable etching of the circuit pattern causes circuit pattern width erosion and undercut of the circuit pattern and the associated undesirable consequences.